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| HT32F0008 datasheet 32-bit arm ? cortex ? -m0+ microcontroller, up to 64 kb flash and 16 kb sram with aes-128, pdma, div, usart, uart, spi, i 2 c, gptm, bftm, pwm, crc, rtc, wdt and usb2.0 fs revision: v1.00 date: ?an?a?? 11? ?01? ?an?a?? 11? ?01?
rev. 1.00 ? of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? table of contents table of contents 1 general description ................................................................................................ 6 2 features ................................................................................................................... 7 co?e ....................................................................................................................................... 7 on-chip memo?? .................................................................................................................... 7 flash memo?? cont?olle? C fmc ............................................................................................ 7 reset cont?ol unit C rstcu ................................................................................................. ? clock cont?ol unit C ckcu .................................................................................................... ? powe? management C pwrcu ............................................................................................. ? exte?nal inte???pt/event cont?olle? C exti ............................................................................ 9 i/o po?ts C gpio .................................................................................................................... 9 pwm gene?ation and capt?? e time?s C gptm .................................................................... 9 p?lse width mod?lation C pwm .......................................................................................... 10 basic f? nction time? C bftm ............................................................................................. 10 watchdog time ? C wdt ....................................................................................................... 10 real time clock C rtc ....................................................................................................... 11 inte?-integ?ated ci?c?it C i ? c ................................................................................................ 11 se?ial pe?iphe?al inte?face C spi ......................................................................................... 11 unive?sal s?nch?ono? s as?nch?ono?s receive? t ?ansmitte? C usart .............................. 1? unive? sal as?nch?ono?s receive? t ?ansmitte? C uart ...................................................... 1? c?clic red?ndanc? check C crc ....................................................................................... 13 pe?iphe?al di?ect memo?? access C pdma ......................................................................... 13 ha?dwa?e divide? C div ....................................................................................................... 13 unive?sal se?ial b?s device cont?olle? C usb .................................................................... 14 advanced enc??ption standa? d C aes-1?? ......................................................................... 14 deb?g s?ppo?t ..................................................................................................................... 14 package and ope? ation tempe?at??e .................................................................................. 14 3 overview ................................................................................................................ 15 device info?mation ............................................................................................................... 15 block diag?am ..................................................................................................................... 16 memo?? map ........................................................................................................................ 17 clock st??ct??e .................................................................................................................... ?0 4 pin assignment ..................................................................................................... 21 5 electrical characteristics ..................................................................................... 29 absol?te maxim?m ratings ................................................................................................. ?9 recommended dc ope?ating conditions ........................................................................... ?9 rev. 1.00 3 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? table of contents table of contents on-chip ldo voltage reg ?lato? cha?acte?istics ................................................................. ?9 powe? cons?mption ............................................................................................................ 30 reset and s?ppl? monito? cha?acte?istics ........................................................................... 3? exte?nal clock cha?acte?istics ............................................................................................. 33 inte?nal clock cha?acte?istics .............................................................................................. 34 pll cha ?acte?istics .............................................................................................................. 34 usb pll cha ?acte?istics ..................................................................................................... 35 memo?? cha?acte?istics ....................................................................................................... 35 i/o po?t cha?acte?istics ........................................................................................................ 35 pwm/gptm cha?acte?istics ................................................................................................ 36 i ? c cha?acte?istics ............................................................................................................... 37 spi cha?acte?istics .............................................................................................................. 3? usb cha?acte?istics ............................................................................................................. 40 6 package information ............................................................................................ 41 saw t ?pe ?4-pin qfn (3mm3mm0.55mm) o?tline dimensions .................................... 4? saw t ?pe 33-pin qfn (4mm4mm) o?tline dimensions ................................................... 43 saw t ?pe 46-pin qfn (6.5mm4.5mm) o?tline dimensions ............................................. 44 4? -pin lqfp (7mm7mm) o?tline dimensions ................................................................... 45 rev. 1.00 4 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? list of tables list of tables table 1. feat ??es and pe?iphe?al list ..................................................................................................... 15 table ?. registe? map ............................................................................................................................ 1? table 3. pin assignment fo ? ?4/33/46-pin qfn? 4? -pin lqfp package ................................................. ?5 table 4. pin desc ?iption .......................................................................................................................... ?7 table 5. absol ?te maxim?m ratings ....................................................................................................... ?9 table 6. recommended dc ope ?ating conditions ................................................................................. ?9 table 7. ldo cha ?acte?istics .................................................................................................................. ?9 table ?. powe? cons?mption cha?acte?istics ......................................................................................... 30 table 9. v dd powe? reset cha?acte?istics .............................................................................................. 3? table 10. lvd/bod cha ?acte?istics ........................................................................................................ 3? table 11. high speed exte ?nal clock (hse) cha?acte?istics .................................................................. 33 table 1 ?. low speed exte?nal clock (lse) cha?acte?istics ................................................................... 33 table 13. high speed inte ?nal clock (hsi) cha?acte?istics .................................................................... 34 table 14. low speed inte ?nal clock (lsi) cha?acte?istics ...................................................................... 34 table 15. pll cha ?acte?istics ................................................................................................................. 34 table 16. usb pll cha ?acte?istics ......................................................................................................... 35 table 17. flash memo ?? cha?acte?istics ................................................................................................. 35 table 1 ?. i/o po?t cha?acte?istics ........................................................................................................... 35 table 19. gptm cha ?acte?istics ............................................................................................................. 36 table ?0. i ? c cha?acte?istics ................................................................................................................... 37 table ?1. spi cha?acte?istics .................................................................................................................. 3? table ??. usb dc elect?ical cha?acte?istics .......................................................................................... 40 table ? 3. usb ac elect?ical cha?acte?istics ........................................................................................... 40 rev. 1.00 5 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? list of tables list of figures list of figures fig??e 1. block diag?am ......................................................................................................................... 16 fig??e ?. memo?? map ............................................................................................................................ 17 fig??e 3. clock st??ct??e ........................................................................................................................ ?0 fig??e 4. ? 4-pin qfn pin assignment .................................................................................................... ?1 fig?? e 5. 33-pin qfn pin assignment .................................................................................................... ?? fig?? e 6. 46-pin qfn pin assignment .................................................................................................... ?3 fig??e 7. 4? -pin lqfp pin assignment ................................................................................................... ?4 fig??e ?. i ? c timing diag ?ams ................................................................................................................ 37 fig?? e 9. spi timing diag?ams C spi maste? mode ............................................................................... 39 fig?? e 10. spi timing diag?ams C spi slave mode with cpha=1 ......................................................... 39 fig?? e 11. usb signal rise time and fall time and c? oss-point voltage (v crs ) defnition ................... 40 rev. 1.00 6 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? general description 1 general description the holtek HT32F0008 device is a high performance , low power consumption 32-bit microcontroller based around a n arm ? cortex ? -m 0+ processor core. the cortex ? -m 0+ is a next - generation processor core which is tightly coupled with nested vectored interrupt controller (nvic), systick timer , and including advanced debug support. the device operate s at a frequency of up to 60 mhz with a flash accelerator to obtain maximum effciency. it provides up to 64 kb of embedded flash memory for code/data storage and 16 kb of embedded sram memory for system operation and application program usage. a variety of peripherals, such as pdma, aes-128, di v, i 2 c, u s art, uart, s pi , gptm, pwm, crc-16/32, rtc, wdt, usb 2.0 fs, sw-dp (serial wire debug port) , etc. , are also implemented in th e device . several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. the above features ensure that the device is suitable for use in a wide range of applications, especially in areas such as data bridge s , sensor hubs and so on. rev. 1.00 7 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? general description features 2 features core } 32-bit arm ? cortex ? -m0+ processor core } up to 60 mhz operati ng frequency } single-cycle multiplication } integrated nested vectored interrupt controller (nvic) } 24-bit systick timer the cortex ? -m0+ processor is a very low gate count, highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized, low-power processor. the processor is based on the armv6-m architecture and supports thumb ? instruction sets; single-cycle i/o port; hardware multiplier and low latency interrupt respond time. on-chip memory } 64 kb on-chip flash memory for instruction/data and options storage } 16 kb on-chip sram } supports multiple boot modes the arm ? cortex ? -m0+ processor accesses and debug accesses share the single external interface to external ahb peripheral. the processor accesses take priority over debug accesses. the maximum address range of the cortex ? -m0+ is 4 gb since it has a 32-bit bus address width. additionally, a pre-defined memory map is provided by the cortex ? -m0+ processor to reduce the software complexity of repeated implementation by different device vendors. however, some regions are used by the arm ? cortex ? -m0+ system peripherals. refer to the arm ? cortex ? -m0+ technical reference manual for more information. figure 2 shows the memory map of the +7)ghylfhlqfoxglqfrgh650shulskhudodqgrwkhusuhghqhguhlrqv flash memory controller C fmc } } 32-bit word programming with in system programming interface (isp) and in application programming (iap) } flash protection capability to prevent illegal access the flash memory controller, fmc, provides all the necessary functions and pre-fetch buffer for the embedded on-chip flash memory. since the access speed of the flash memory is slower than the cpu, a wide access interface with a pre-fetch buffer and cache are provided for the flash memory in order to reduce the cpu waiting time which will cause cpu instruction execution delays. flash memory word program/page erase functions are also provided. rev. 1.00 ? of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? features reset control unit C rstcu } supply supervisor: power on reset / power down reset C por/pdr brown-out detector C bod programmable low voltage detector C lvd the reset control unit , rstcu , has three kinds of reset, a power on reset, a system reset and an apb unit reset. the power on reset, known as a cold reset, resets the full system during power up. a system reset resets the processor core and peripheral ip components with the exception of the sw-dp controller. the resets can be triggered by an external signal, internal events and the reset generators. clock control unit C ckcu } external 4 to 16 mhz crystal oscillator } external 32,768 hz crystal oscillator } internal 8 mhz rc oscillator trimmed to 2 % accuracy at 3.3 v operating voltage and 25 & operating temperature } internal 32 khz rc oscillator } integrated system clock pll and usb pll } independent clock divider and gating bits for peripheral clock sources the clock control unit, ckcu, provides a range of oscillator and clock functions. these include a high speed internal rc oscillator (hsi), a high speed external crystal oscillator (hse), a low speed internal rc oscillator (lsi), a low speed external crystal oscillator (lse), a phase lock loop (pll), a hse clock monitor, clock prescalers, clock multiplexers, apb clock divider and gating circuitry. the ahb, apb and cortex ? -m0+ clocks are derived from the system clock (ck_sys) which can come from the hsi, hse or pll. the watchdog timer and real time clock (rtc) use either the lsi or lse as their clock source. power management C pwrcu } single v dd power supply: 1.65 v to 3.6 v } integrated 1.5 v ldo regulator for cpu core, peripherals and memories power supply } v dd power supply for rtc } two power domains: v dd , 1.5 v } four power saving modes: sleep, deep-sleep1, deep-sleep2, power-down power consumption can be regarded as one of the most important issues for many embedded system applications. accordingly the power control unit, pwrcu, in the device provides many types of power saving modes such as sleep, deep-sleep1, deep-sleep2 and power-down mode. these operating modes reduce the power consumption and allow the application to achieve the best wudghriiehwhhqwkhfrqlfwlqghpdqgvri&38rshudwlqwlphvshhgdqgsrhufrqvxpswlrq rev. 1.00 9 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? features features external interrupt/event controller C exti } } all gpio pins can be selected as exti trigger source } source trigger type includes high level, low level, negative edge, positive edge, or both edge } individual interrupt enable, wakeup enable and status bits for each exti line } software interrupt trigger mode for each exti line } the external interrupt/event controller, exti, comprises 16 edge detectors which can generate a wake-up event or interrupt requests independently. each exti line can also be masked independently. i/o ports C gpio } up to 42 gpios } port a, b, c, f are mapped as 16 external interrupts C exti } there are up to 42 general purpose i/o pins, gpio, named from pa0 ~ pa15 to pc0 ~ pc7 and pf0 ~ pf1 for the implementation of logic input/output functions. each of the gpio ports has a series of related control and configuration registers to maximize flexibility and to meet the requirements of a wide range of applications. the gpio ports are pin-shared with other alternative functions to obtain maximum functional flexibility on the package pins. the gpio pins can be used as alternative functional pins by configuring the corresponding registers regardless of the input or output pins. the external lqwhuuxswvrqwkh3,2slqvriwkhghylfhkdyhuhodwhgfrqwurodqgfrqxudwlrquhlvwhuvlqwkh external interrupt control unit , exti. pwm generation and capture timers C gptm } 16-bit up, down, up/down auto-reload counter } 16-bit programmable prescaler allowing counter clock frequency division by any factor between 1 and 65536 } input capture function } compare match output } pwm waveform generation with edge-aligned and center-aligned counting modes } single pulse mode output } encoder interface controller with two inputs using quadrature decoder the general purpose timer consists of one 16-bit up/down-counter, four 16-bit capture/compare registers (ccrs), one 16-bit counter reload register (crr) and several control/status registers. they can be used for a variety of purposes including general time measurement, input signal pulse width measurement, output waveform generation such as single pulse generation, or pwm output generation. the gptm supports an encoder interface using a decoder with two inputs. rev. 1.00 10 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? features pulse width modulation C pwm } 16-bit up and auto-reload counter } up to 4 independent channels for each timer } 16-bit programmable prescaler allowing counter clock frequency division by any factor between 1 and 65536 } compare match output } pwm waveform generation with edge-aligned and center-aligned counting modes } single pulse mode output the pulse width modulator consists of one 16-bit up/down-counter, four 16-bit compare registers (crs), one 16-bit counter-reload register (crr) and several control/status registers. it can be used for a variety of purposes including general timer and output waveform generation such as single pulse generation or pwm output. basic function timer C bftm } 32-bit compare/match count-up counter C no i/o control features } one shot mode C counting stops after a match condition } repetitive mode C restart counter after a match condition the basic function timer is a simple count-up 32-bit counter designed to measure time intervals and generate a one shot or repetitive interrupts. the bftm operates in two functional modes, repetitive or one shot mode. in the repetitive mode the bftm restarts the counter when a compare match event occurs. the bftm also supports a one shot mode which forces the counter to stop counting when a compare match event occurs. watchdog timer C wdt } 12-bit down counter with 3-bit prescaler } reset event for the system } programmable watchdog timer window function } register write protection function the watchdog timer is a hardware timing circuit that can be used to detect system failures due to software malfunctions. it includes a 12-bit count-down counter, a prescaler, a wdt delta value register, wdt operation control circuitry and a wdt protection mechanism. if the software does qrwuhordgwkhfrxqwhuydoxhehiruhd:dwfkgr7lphuxqghurrffxuvduhvhwlooehhqhudwhg when the counter underflows. in addition, a reset is also generated if the software reloads the counter when the counter value is greater than the wdt delta value. this means the counter must ehuhordghglwklqdolplwhgwlplqlqgrxvlqdvshflfphwkrg7kh:dwfkgr7lphufrxqwhu can be stopped while the processor is in the debug mode. there is a register write protect function klfkfdqehhqdeohgwrsuhyhqwlwiurpfkdqlqwkh:dwfkgr7lphufrqxudwlrqxqhshfwhgo rev. 1.00 11 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? features features real time clock C rtc } 24-bit up-counter with a programmable prescaler } alarm function } interrupt and wake-up event the real time clock, rtc, includes an apb interface, a 24-bit count- up counter, a control register, a prescaler, a compare register and a status register. most of the rtc circuits are located in the backup domain except for the apb interface. the apb interface is located in the v dd15 power domain. therefore, it is necessary to be isolated from the iso signal that comes from the power control unit when the v dd15 power domain is powered off, that is when the device enters the power- down mode. the rtc counter is used as a wakeup timer to generate a system resume signal from the power-down mode. inter-integrated circuit C i 2 c } supports both master and slave modes with a frequency of up to 1 mhz } provide an arbitration function and clock synchronization } supports 7-bit and 10-bit addressing modes and general call addressing } supports slave multi-addressing mode with maskable address the i 2 c is an internal circuit allowing communication with an external i 2 c interface which is an industry standard two line serial interface used for connection to external hardware. these two serial lines are known as a serial data line, sda, and a serial clock line, scl. the i 2 c module provides three data transfer rates: (1) 100 khz in the standard mode, (2) 400 khz in the fast mode and (3) 1 mhz in the fast plus mode . the scl period generation register is used to setup different kinds of duty cycle implementation s for the scl pulse. the sda line which is connected directly to the i 2 c bus is a bi-directional data line between the master and slave devices and is used for data transmission and reception. the i 2 c also has an arbitration detect function and clock synchronization to prevent situation s where more than one master attempts to transmit data to the i 2 c bus at the same time. serial peripheral interface C spi } supports both master and slave mode } frequency of up to (f pclk /2) mhz for the master mode and (f pclk /3) mhz for the slave mode } fifo depth: 8 levels } multi-master and multi-slave operation the serial peripheral interface, spi, provides an spi protocol data transmit and receive function in both master and slave mode. the spi interface uses 4 pins, which are the serial data input and output lines miso and mosi, the clock line, sck, and the slave select line, sel. one spi device dfwvdvdpdvwhughylfhklfkfrqwurovwkhgdwdrxvlqwkh6(/dqg6&.vlqdovwrlqglfdwhwkh start of data communication and the data sampling rate. to receive a data byte, the streamed data elwvduhodwfkhgrqdvshflfforfnhghdqgvwruhglqwkhgdwduhlvwhurulqwkh5;),)2dwd transmission is carried out in a similar way but in a reverse sequence. the mode fault detection provides a capability for multi-master applications. rev. 1.00 1? of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? features universal synchronous asynchronous receiver transmitter C usart } supports both asynchronous and clocked synchronous serial communication modes } asynchronous operating baud rate clock frequency up to (f pclk /16) mhz and synchronous oper - ating rate clock frequency up to (f pclk /8) mhz } f ull duplex communication } fully programmable serial communication characteristics including: word length: 7, 8, or 9-bit character parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation %lwrughu/6%uvwru06%uvwwudqvihu } error detection: parity, overrun, and frame error } } irda sir encoder and decoder } rs485 mode with output enable control } fifo depth: 8 9 bits for both receiver and transmitter 7kh8qlyhuvdo6qfkurqrxvvqfkurqrxv5hfhlyhu7udqvfhlyhu8657surylghvdhleohixoo duplex data exchange using synchronous or asynchronous data transfer. the usart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the usart peripheral function supports four types of interrupt including line status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt and time out interrupt. the usart module includes a transmitter fifo, (tx_fifo) and receiver fifo (rx_fifo). the software can detect a usart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions resulting from parity, overrun, framing and break events. universal asynchronous receiver transmitter C uart } asynchronous serial communication operating baud rate clock frequency up to (f pclk /16) mhz } f ull duplex communication } fully programmable serial communication characteristics including: word length: 7, 8, or 9-bit character parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation %lwrughu/6%uvwru06%uvwwudqvihu } error detection: parity, overrun, and frame error the universal asynchronous receiver transceiver, uart, provides a flexible full duplex data exchange using asynchronous transfer. the uart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the uart peripheral function supports line status interrupt. the software can detect a uart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions resulting from parity, overrun, framing and break events. rev. 1.00 13 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? features features cyclic redundancy check C crc } support crc16 polynomial: 0x8005, x 16 +x 15 +x 2 +1 } support ccitt crc16 polynomial: 0x1021, x 16 +x 12 +x 5 +1 } support ieee-802.3 crc32 polynomial: 0x04c11db7, x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1 } supports 1s complement, byte reverse & bit reverse operation on data and checksum } supports byte, half-word & word data size } programmable crc initial seed value } crc computation executed in 1 ahb clock cycle for 8-bit data and 4 ahb clock cycles for 32-bit data } supports pdma to complete a crc computation of a block of memory the crc calculation unit is an error detection technique test algorithm which is used to verify data transmission or storage data correctness. a crc calculation takes a data stream or a block of data as its input and generates a 16-bit or 32-bit output remainder. ordinarily, a data stream is vxihged&5&frghdqgxvhgdvdfkhfnvxpkhqehlqvhqwruvwruhg7khuhiruhwkhuhfhlyhg or restored data stream is calculated by the same generator polynomial as described above. if the new crc code result does not match the one calculated earlier, then this means that the data stream contains a data error. peripheral direct memory access C pdma } 6 channels with trigger source grouping } 8-/16-/32-bit width data transfer } } 4-level programmable channel priority } auto reload mode } supports trigger source: spi, usart, uart, i 2 c, gptm, pwm, aes and software request the peripheral direct memory access controller, pdma, moves data between the peripherals and the system memory on the ahb bus. each pdma channel has a source address, destination address, block length and transfer count. the pdma can exclude the cpu intervention and avoid interrupt service routine execution. it improves system performance as the software does not need to connect each data movement operation. hardware divider C div } signed/unsigned 32-bit divider } operation in 8 clock cycles, load in 1 clock cycle. } divide by zero error flag. the divider is the truncated division and need software trigger start single by control register rev. 1.00 14 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? features start bit , after 8 clock cycles, the divider calculate complete fag will be set to 1, and if divisor register data is zero, divide zero error fag will be set to 1. universal serial bus device controller C usb complies with usb 2.0 full-speed (12 mbps) specifcation on-chip usb full-speed transceiver 1 control endpoint (ep0) for control transfer 3 single-buffered endpoints for bulk and interrupt transfer 4 double-buffered endpoints for bulk, interrupt and isochronous transfer 1,024 bytes ep_sram used as the endpoint data buffers the usb device controller is compliant with the usb 2.0 full-speed specifcation. there is one control endpoint known as endpoint 0 and seven configurable endpoints. a 1024-byte sram is used as the endpoint buffer. each endpoint buffer size is programmable using corresponding registers, which provides maximum fexibility for various applications. the integrated usb full- speed transceiver helps to minimize the overall system complexity and cost. the usb functional block also contains the resume and suspend feature to meet the requirements of low-power consumption. advanced encryption standard C aes-128 supports aes encrypt / decrypt function supports aes ecb/cbc/ctr mode supports key size 128 bits supports 4 words initial vector for cbc and ctr mode 4 32 bits aes data buffer supports dma interface supports word data swap function the aes core supports encryption and decryption function. aes only supports 128 bits input data to do encryption or decryption. hardware does not pad any bits of input data. software need to do pad action at frst. debug support serial wire debug port C sw-dp 4 comparators for hardware breakpoint or code / literal patch 2 comparators for hardware watchpoints package and operation temperature 24/33/46-pin qfn, 48-pin lqfp package operation temperature range: -40 ?c to +85 ?c rev. 1.00 15 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? features overview 3 overview device information table 1. features and peripheral list peripherals HT32F0008 main flash (kb) 63 option b?tes flash (kb) 1 sram (kb) 16 time ? gptm 1 pwm ? bftm ? rtc 1 wdt 1 comm?nication usb 1 spi 1 usart 1 uart 1 i ? c 1 crc-16/3? 1 div 1 pdma 6 channels aes-1?? 1 exti 16 gpio up to 4? cpu f?eq?enc? up to 60 mhz ope? ating voltage 1.65 v ~ 3.6 v ope? ating tempe?at??e -40 ?c ~ 85 ?c package ?4/33/46-pin qfn 4?-pin lqfp rev. 1.00 16 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? overview block diagram sw-dp apb ahb pe?iphe?als flash memo?? co?tex ? -m0+ p?ocesso? s?stem nvic sram cont?olle? fmc cont?ol registe?s ckcu/rstcu cont?ol registe?s pdma cont?ol registe?s pdma 6 channels dma ?eq?est inte???pt ?eq?est afio exti ch0 ~ ch3 boot clock and ?eset cont?ol powe? cont?ol b?s mat?ix af af af af powe?ed b? v dd15 swclk swdio sda scl af powe? s?ppl?: b?s: cont?ol signal: alte?nate f?nction: af mosi? miso sck? sel af flash memo?? inte?face tx? rx rts/txe cts/sck x3?kin x3?kout af lsi 3? khz lse 3??76? hz v dd v ss rtc pwrcu nrst rtcout wakeup af af i ? c pwm0 ~ 1 bftm0 ~ 1 ahb to apb b?idge wdt gpio pa ~ pb[15:0]? pc[7:0]? pf[1:0] af tx? rx crc -16/3? ch0 ~ch3 af io po?t uart spi powe?ed b? v dd v ss v dd por /pdr bod lvd xtalin xtalout hsi ? mhz hse 4 ~ 16 mhz af ldo 1.5 v gptm cldo cap. usart powe?ed b? v dd15 pll f max : 60 mhz aes -1?? powe?ed b? v dd usb cont?ol/data registe?s divide? usb device af dp dm usb pll f: 4? mhz sram figure 1. block diagram rev. 1.00 17 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? overview overview memory map rese?ved ep_sram usb rese?ved rese?ved gpio a ~ c rese?ved rese?ved rese?ved bftm1 bftm0 gptm rtc & pwrcu rese?ved rese?ved rese?ved rese?ved rese?ved rese?ved 0x400?_?000 rese?ved 64 kb on-chip flash 0x0000_0000 rese?ved 0x0001_0000 boot loade? 0x1f00_0000 rese?ved 0x1f00_0?00 option b?te alias 0x1ff0_0000 64 kb ? kb 1 kb rese?ved 0x1ff0_0400 code sram pe?iphe?al 16 kb on-chip sram 0x?000_0000 rese?ved 0x?000_4000 16 kb apb pe?iphe?als 0x4000_0000 ahb pe?iphe?als 0x400?_0000 0x4010_0000 p?ivate pe?iphe?al b?s 0xe000_0000 rese?ved 0xe010_0000 0xffff_ffff 51? kb 51? kb usart 0x4000_0000 uart 0x4000_1000 spi 0x4000_4000 0x4000_5000 i ? c exti 0x400?_3000 afio 0x400?_4000 wdt 0x4004_?000 0x4003_1000 0x4006_9000 0x4003_?000 0x4006_b000 0x4006_a000 0x4004_9000 0x4006_e000 apb fmc 0x400?_0000 rese?ved 0x400?_?000 ckcu/rstcu 0x400?_?000 crc 0x400?_a000 0x400f_ffff ahb 0x4000_?000 0x400?_5000 0x4009_?000 0x400b_0000 0x400c_c000 0x4006_?000 0x4006_f000 0x4007_6000 0x4007_7000 0x4007_?000 pwm0 rese?ved pwm1 rese?ved pdma 0x400?_c000 rese?ved 0x4009_0000 rese?ved gpio f aes 0x400c_?000 rese?ved div 0x400a_?000 0x400a_a000 0x400a_c000 0x4007_1000 0x4007_?000 0x400b_c000 0x400b_a000 0x400b_6000 0x400c_a000 figure 2. memory map rev. 1.00 1? of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? overview table 2. register map start address end address peripheral bus 0x4000_0000 0x4000_0fff usart apb 0x4000_1000 0x4000_1fff uart 0x4000_?000 0x4000_3fff rese?ved 0x4000_4000 0x4000_4fff spi 0x4000_5000 0x400?_1fff rese?ved 0x400?_?000 0x400?_?fff afio 0x400?_3000 0x400?_3fff rese?ved 0x400?_4000 0x400?_4fff exti 0x400?_5000 0x4003_0fff rese?ved 0x4003_1000 0x4003_1fff pwm0 0x4003_?000 0x4004_7fff rese?ved 0x4004_?000 0x4004_?fff i ? c 0x4004_9000 0x4006_7fff rese?ved 0x4006_?000 0x4006_?fff wdt 0x4006_9000 0x4006_9fff rese?ved 0x4006_a000 0x4006_afff rtc/pwrcu 0x4006_b000 0x4006_dfff rese?ved 0x4006_e000 0x4006_efff gptm 0x4006_f000 0x4007_0fff rese?ved 0x4007_1000 0x4007_1fff pwm1 0x4007_?000 0x4007_5fff rese?ved 0x4007_6000 0x4007_6fff bftm0 0x4007_7000 0x4007_7fff bftm1 0x4007_?000 0x4007_ffff rese?ved rev. 1.00 19 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? overview overview start address end address peripheral bus 0x400?_0000 0x400?_1fff fmc ahb 0x400?_?000 0x400?_7fff rese?ved 0x400?_?000 0x400?_9fff ckcu/rstcu 0x400?_a000 0x400?_bfff crc 0x400?_c000 0x400?_ffff rese?ved 0x4009_0000 0x4009_1fff pdma 0x4009_?000 0x400a_7fff rese?ved 0x400a_?000 0x400a_bfff usb 0x400a_c000 0x400a_ffff rese?ved 0x400b_0000 0x400b_1fff gpio a 0x400b_?000 0x400b_3fff gpio b 0x400b_4000 0x400b_5fff gpio c 0x400b_6000 0x400b_9fff rese?ved 0x400b_a000 0x400b_bfff gpio f 0x400b_c000 0x400c_7fff rese?ved 0x400c_?000 0x400c_9fff aes 0x400c_a000 0x400c_bfff div 0x400c_c000 0x400f_ffff rese?ved rev. 1.00 ?0 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? overview clock structure 4-16 mhz hse xtal ? mhz hsi rc 3? khz lsi rc legend: hse = high speed exte?nal clock hsi = high speed inte?nal clock lse = low speed exte?nal clock lsi = low speed inte?nal clock 3?.76? khz lse osc wdtsrc pllsrc ahb p?escale? 1???4???16?3? fclk ( f?ee ??nning clock) stclk (to s?stick) ck_wdt wdten ck_ref ck_hsi/16 ck_hse/16 ck_sys/16 ckout ckoutsrc[?:0] hseen hsien lseen (note1) lsien (note1) ck_lsi ck_lse ck_ahb/16 ck_hsi ck_hse pclk (afio? spi? usart? uart? i ? c? gptm? pwmx? bftmx? exti? rtc? wdt) s?stem pll clock monito? pllen ck_lse ck_pll f ck_pll,max = 60 mhz ck_lsi hclks ( to sram) hclkf ( to flash) cm0pen fmcen cm0pen sramen 1 0 rtcsrc (1) ck_rtc rtcen (1) 1 0 1 0 ck_ahb 000 001 010 011 100 101 110 ck_sys sw[?:0] ? hclkc ( to co?tex ? -m0+) cm0pen (cont?ol b? hw) hclkbm ( to b?s mat?ix) cm0pen bmen hclkapb ( to apb b?idge) cm0pen apben ck_crc ( to crc) crcen pe?iphe?als clock p?escale? 1???4?? 00 01 10 11 pclk pclk/? pclk/4 pclk/? spien i?cen ck_gpio ( to gpio po?t) gpiocen gpioaen hsi a?to t?imming cont?olle? ck_lse usb ref p?lse 00x 011 010 111 110 ck_usb f ck_usb = 48 mhz usben p?escale? 1 ~ 3? ck_ref divide? ? ckrefen usbpllsrc usb pll usbpllen 1 0 usbsrc 0 1 ckrefpre ck_usbpll hclkd ( to pdma) dmaen ck_div ( to div) diven ck_aes ( to aes) aesen gpiofen figure 3. clock structure rev. 1.00 ?1 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? overview pin assignment 4 pin assignment vss pf0 pb? pb7 pb? pb3 ?4 ?3 ?? ?1 ?0 7 ? 9 10 11 1? 1? 17 16 15 14 pb1 pb0 pa9_ boot xtalin af0 (defa?lt) af0 (defa?lt) af0 (defa?lt) vdd vss nrst pb1? p33 vdd 33v vdd 33v p15 HT32F0008 24 qfn-a 19 cldo af0 (defa?lt) p33 33v 33v 33v 33v swclk swdio pa1? pa13 pb13 af1 af1 33v 33v 33v 33v 33v 33v 13 xtalout pb14 33v ep: vss 1 ? 3 4 5 6 pa0 pa1 pa? pa3 usbdm /pc6 usbdp /pc7 33v 33v 33v 33v p33 33v usb usb 3.3 v digital & analog io pad p33 p15 33v 33v 3.3 v digital powe? pad usb phy pad 1.5 v powe? pad 3.3 v digital i/o pad vdd vdd domain pad usb figure 4. 24-pin qfn pin assignment rev. 1.00 ?? of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? pin assignment pf1 pb5 pf0 pb? pb7 pb4 pb? pb3 3? 31 30 ?9 ?? ?7 ?6 9 10 11 1? 13 14 15 16 ?4 ?3 ?? ?1 ?0 19 1? pb1 pb0 pa15 pa14 pa9_ boot xtalin af0 (defa?lt) af0 (defa?lt) af0 (defa?lt) vdd vss nrst x3?kin x3?kout rtcout p33 vdd 33v vdd 33v vdd 33v vdd 33v p15 HT32F0008 33 qfn-a ?5 cldo af0 (defa?lt) p33 33v 33v 33v 33v swclk swdio pa1? pa13 pb10 pb11 pb1? pb13 af1 af1 33v 33v 33v 33v 33v 33v 33v 33v 33v 17 xtalout pb14 33v 33 vss 1 ? 3 4 5 6 7 ? pa0 pa1 pa? pa3 pa4 pa5 usbdm /pc6 usbdp /pc7 33v 33v 33v 33v 33v 33v usb usb 33v 33v 33v 3.3 v digital & analog io pad p15 33v 33v 1.5 v powe? pad 3.3 v digital i/o pad vdd vdd domain pad usb usb phy pad p33 3.3 v digital powe? pad figure 5. 33-pin qfn pin assignment rev. 1.00 ?3 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? pin assignment pin assignment pf1 pb6 pf0 pb? pb7 pc3 pc? pc1 pb5 pb4 pb? pb3 45 44 43 4? 41 40 39 3? 37 36 35 1 ? 3 4 5 6 7 ? 10 11 1? 13 14 15 16 17 1? 19 ?0 3? 31 30 ?9 ?? ?7 ?6 ?5 ?4 pa1 pa? pa3 pa4 pa5 pa6 pa7 usbdm /pc6 usbdp /pc7 vdd_? pb1 pb0 pa15 pa14 pa10 xtalin af0 (defa?lt) af0 (defa?lt) af0 (defa?lt) vdd_1 vss_1 nrst pb9 x3?kin x3?kout rtcout pc0 xtalout pb15 p33 vdd 33v vdd 33v vdd 33v vdd 33v vdd 33v p15 33v 33v 33v 33v 33v 33v 33v HT32F0008 46 qfn-a 34 9 ?1 cldo af0 (defa?lt) p33 33v 33v p33 p33 33v 33v 33v swclk swdio pa1? pa13 pb10 pb11 pb1? pb13 pb14 af1 af1 pa11 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v pa0 46 33v pa? ?? 33v pa9_boot ?3 33v vss_? 33 33v 33v 33v 33v usb usb 33v 33v p33 p15 33v 33v 3.3 v digital powe? pad 1.5 v powe? pad 3.3 v digital & analog io pad 3.3 v digital i/o pad vdd vdd domain pad usb usb phy pad figure 6. 46-pin qfn pin assignment rev. 1.00 ?4 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? pin assignment pf1 pb6 pf0 pb? pb7 pc3 pc? pc1 pb5 pb4 pb? pb3 4? 47 46 45 44 43 4? 41 40 39 3? 1 ? 3 4 5 6 7 ? 9 10 11 13 14 15 16 17 1? 19 ?0 ?1 ?? ?3 35 34 33 3? 31 30 ?9 ?? ?7 ?6 ?5 pa0 pa1 pa? pa3 pa4 pa5 pa6 pa7 pc4 usbdm /pc6 usbdp /pc7 vss_? vdd_? pb1 pb0 pa15 pa14 pa10 pa9_ boot pa? xtalin af0 (defa?lt) af0 (defa?lt) af0 (defa?lt) vdd_1 vss_1 nrst pb9 x3?kin x3?kout rtcout pc0 xtalout pb15 p33 vdd 33v vdd 33v vdd 33v vdd 33v vdd 33v p15 usb usb 33v 33v 33v 33v 33v 33v 33v HT32F0008 48 lqfp-a 37 1? ?4 36 cldo af0 (defa?lt) 33v pc5 p33 33v 33v p33 p33 33v 33v 33v swclk swdio pa1? pa13 pb10 pb11 pb1? pb13 pb14 af1 af1 pa11 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v p33 p15 33v 33v 3.3 v digital powe? pad 1.5 v powe? pad 3.3 v digital & analog io pad 3.3 v digital i/o pad usb usb phy pad vdd vdd domain pad figure 7. 48-pin lqfp pin assignment rev. 1.00 ?5 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? pin assignment pin assignment table 3. pin assignment for 24/33/46-pin qfn, 48-pin lqfp package package alternate function mapping af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 48 lqfp 46 qfn 33 qfn 24 qfn system default gpio n/a n/a gptm /pwm spi usart /uart i2c n/a n/a n/a n/a n/a n/a n/a system other 1 46 1 1 pa0 gt_ ch0 spi_ sck usr_ rts i?c_ scl ? 1 ? ? pa1 gt_ ch1 spi_ mosi usr_ cts i?c_ sda 3 ? 3 3 pa ? gt_ ch? spi_ miso usr_ tx 4 3 4 4 pa3 gt_ ch3 spi_ sel usr_ rx 5 4 5 pa4 gt_ ch0 spi_ sck ur_tx i?c_ scl 6 5 6 pa5 gt_ ch1 spi_ mosi ur_rx i?c_ sda 7 6 pa6 gt_ ch? spi_ miso ? 7 pa7 gt_ ch3 spi_ sel 9 pc4 pwm1_ ch0 usr_ tx 10 pc5 pwm1_ ch1 usr_ rx 11 ? 7 5 pc6 gt_ ch0 usr_ tx i?c_ scl 11 ? 7 5 usbdm 1? 9 ? 6 usbdp 1? 9 ? 6 pc7 gt_ ch1 usr_ rx i?c_ sda 13 10 9 7 cldo 14 11 10 ? vdd_? 15 1? 11 9 vss_? 16 13 1? 10 nrst 17 14 pb9 pwm1_ ch? 1? 15 13 x3?kin pb10 gt_ ch0 spi_ sel usr_ tx 19 16 14 x3?kout pb11 gt_ ch1 spi_ sck usr_ rx ?0 17 15 11 rtcout pb1? pwm0_ ch0 spi_ miso ur_rx wakeup ?1 1? 16 1? xtalin pb13 ur_tx i?c_ scl ?? 19 17 13 xtalout pb14 ur_rx i?c_ sda ?3 ?0 pb15 pwm0_ ch1 spi_ sel i?c_ scl ?4 ?1 pc0 pwm0_ ch? spi_ sck i?c_ sda ?5 ?? pa ? pwm1_ ch3 usr_ tx ?6 ?3 1? 14 pa9_ boot pwm1_ ch0 spi_ mosi ckout ?7 ?4 pa10 pwm0_ ch1 spi_ mosi usr_ rx rev. 1.00 ?6 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? pin assignment package alternate function mapping af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 48 lqfp 46 qfn 33 qfn 24 qfn system default gpio n/a n/a gptm /pwm spi usart /uart i2c n/a n/a n/a n/a n/a n/a n/a system other ?? ?5 pa11 pwm0_ ch? spi_ miso ?9 ?6 19 15 swclk pa1 ? 30 ?7 ?0 16 swdio pa13 31 ?? ?1 pa14 pwm0_ ch0 spi_ sel usr_ rts i?c_ scl 3? ?9 ?? pa15 pwm1_ ch? spi_ sck usr_ cts i?c_ sda 33 30 ?3 17 pb0 pwm0_ ch1 spi_ mosi usr_ tx i?c_ scl 34 31 ?4 1? pb1 pwm1_ ch1 spi_ miso usr_ rx i?c_ sda 35 3? vdd_? 36 33 33 ?1 vss_? 37 34 ?5 19 pb? pwm0_ ch? spi_ sel ur_tx ckin 3? 35 ?6 ?0 pb3 pwm1_ ch? spi_ sck ur_rx 39 36 ?7 pb4 pwm0_ ch3 spi_ mosi ur_tx 40 37 ?? pb5 gt_ ch? spi_ miso ur_rx 41 3? pc1 pwm0_ ch0 spi_ sel ur_tx 4? 39 pc? pwm1_ ch0 spi_ sck 43 40 pc3 pwm1_ ch1 spi_ mosi ur_rx 44 41 pb6 gt_ ch3 spi_ miso ur_tx 45 4? ?9 ?? pb7 pwm0_ ch3 spi_ miso ur_tx i?c_ scl 46 43 30 ?3 pb? pwm1_ ch3 spi_ sel ur_rx i?c_ sda 47 44 31 ?4 pf0 gt_ ch? 4? 45 3? pf1 gt_ ch3 note: the pin n ?mbe? 33 of the 33qfn is located at the exposed pad of the qfn package. rev. 1.00 ?7 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? pin assignment pin assignment table 4. pin description pin number pin name type (1) io structure (2) output driving description 48 lqfp 46 qfn 33 qfn 24 qfn default function (af0) 1 46 1 1 pa0 i/o 33v 4/?/1?/16 ma pa0 ? 1 ? ? pa1 i/o 33v 4/?/1?/16 ma pa1 3 ? 3 3 pa ? i/o 33v 4/?/1?/16 ma pa ? 4 3 4 4 pa3 i/o 33v 4/?/1?/16 ma pa3 5 4 5 pa4 i/o 33v 4/?/1?/16 ma pa4 6 5 6 pa5 i/o 33v 4/?/1?/16 ma pa5 7 6 pa6 i/o 33v 4/?/1?/16 ma pa6 ? 7 pa7 i/o 33v 4/?/1?/16 ma pa7 9 pc4 i/o 33v 4/?/1?/16 ma pc4 10 pc5 i/o 33v 4/?/1?/16 ma pc5 11 ? 5 pc6 i/o 33v 4/?/1?/16 ma pc6 11 ? 7 5 usbdm ai/o usb diffe ?ential data b?s confo?ming to the unive?sal se?ial b?s standa?d. 1? 9 ? 6 usbdp ai/o usb diffe ?ential data b?s confo?ming to the unive?sal se?ial b?s standa?d. 1? 9 6 pc7 i/o 33v 4/?/1?/16 ma pc7 13 10 9 7 cldo p co?e powe? ldo 1.5 v o?tp?t it is ?ecommended to connect a 2.2 f capacitor as close as possible between this pin and vss_1. 14 11 10 ? vdd_1 p voltage fo ? digital i/o 15 1? 11 9 vss_1 p g?o?nd ?efe?ence fo? digital i/o 16 13 1? 10 nrst (3) i 33v_pu exte?nal ?eset pin and exte?nal wake?p pin in the powe?-down mode 17 14 pb9 (3) i/o (v dd ) 33v 4/?/1?/16 ma pb9 1? 15 13 pb10 (3) ai/o (v dd ) 33v 4/?/1?/16 ma x3?kin 19 16 14 pb11 (3) ai/o (v dd ) 33v 4/?/1?/16 ma x3?kout ?0 17 15 11 pb1? (3) i/o (v dd ) 33v 4/?/1?/16 ma rtcout ?1 1? 16 1? pb13 ai/o 33v 4/?/1?/16 ma xtalin ?? 19 17 13 pb14 ai/o 33v 4/?/1?/16 ma xtalout ?3 ?0 pb15 i/o 33v 4/?/1?/16 ma pb15 ?4 ?1 pc0 i/o 33v 4/?/1?/16 ma pc0 ?5 ?? pa ? i/o 33v 4/?/1?/16 ma pa ? ?6 ?3 1? 14 pa9 i/o 33v_pu 4/?/1?/16 ma pa9_boot ?7 ?4 pa10 i/o 33v 4/?/1?/16 ma pa10 ?? ?5 pa11 i/o 33v 4/?/1?/16 ma pa11 ?9 ?6 19 15 pa1 ? i/o 33v_pu 4/?/1?/16 ma swclk rev. 1.00 ?? of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? pin assignment pin number pin name type (1) io structure (2) output driving description 48 lqfp 46 qfn 33 qfn 24 qfn default function (af0) 30 ?7 ?0 16 pa13 i/o 33v_pu 4/?/1?/16 ma swdio 31 ?? ?1 pa14 i/o 33v 4/?/1?/16 ma pa14 3? ?9 ?? pa15 i/o 33v 4/?/1?/16 ma pa15 33 30 ?3 17 pb0 i/o 33v 4/?/1?/16 ma pb0 34 31 ?4 1? pb1 i/o 33v 4/?/1?/16 ma pb1 35 3? vdd_? p voltage fo ? digital i/o 36 33 33 ?1 vss_? p g?o?nd ?efe?ence fo? digital i/o 37 34 ?5 19 pb? i/o 33v 4/?/1?/16 ma pb? 3? 35 ?6 ?0 pb3 i/o 33v 4/?/1?/16 ma pb3 39 36 ?7 pb4 i/o 33v 4/?/1?/16 ma pb4 40 37 ?? pb5 i/o 33v 4/?/1?/16 ma pb5 41 3? pc1 i/o 33v 4/?/1?/16 ma pc1 4? 39 pc? i/o 33v 4/?/1?/16 ma pc? 43 40 pc3 i/o 33v 4/?/1?/16 ma pc3 44 41 pb6 i/o 33v 4/?/1?/16 ma pb6 45 4? ?9 ?? pb7 i/o 33v 4/?/1?/16 ma pb7 46 43 30 ?3 pb? i/o 33v 4/?/1?/16 ma pb? 47 44 31 ?4 pf0 i/o 33v 4/?/1?/16 ma pf0 4? 45 3? pf1 i/o 33v 4/?/1?/16 ma pf1 note: 1. i = inp?t? o = o?tp?t? a = analog po?t? p = powe? s?ppl ?? pu = p?ll-?p? v dd = v dd powe? . ?. 33 v = 3.3 v tole?ant. 3. these pins a ?e located at the v dd powe? domain. rev. 1.00 ?9 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? pin assignment electrical characteristics 5 electrical characteristics absolute maximum ratings the following table shows the absolute maximum ratings of the device. these are stress ratings only. stresses beyond absolute maximum ratings may cause permanent damage to the device. note that the device is not guaranteed to operate properly at the maximum ratings. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter min. max. unit v dd exte?nal main s?ppl? voltage v ss - 0.3 v ss + 3.6 v v in inp? t voltage on i/o v ss - 0.3 v ss + 0.3 v t a ambient ope? ating tempe?at??e range -40 +?5 ?c t stg sto? age tempe?at?? e range -55 +150 ?c t ? maxim?m ?? nction tempe?at??e +1?5 ?c p d total powe ? dissipation 500 mw v esd elect?ostatic discha? ge voltage C h?man bod? mode -4000 +4000 v recommended dc operating conditions table 6. recommended dc operating conditions t a = 25 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dd i/o ope? ating voltage 1.65 3.3 3.6 v on-chip ldo voltage regulator characteristics table 7. ldo characteristics t a = ?5 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit v ldo inte?nal reg?lato? o?tp?t voltage v dd 1.65 v reg?lato? inp?t @ i ldo = 10 ma and voltage va ?i - ant = 5 %? afte? t?imming 1.4?5 1.5 1.57 v i ldo o?tp?t c???ent v dd = ?.0 ~ 3.6 v reg?lato? inp?t @ v ldo = 1.5 v 30 35 ma v dd = 1.65 ~ ?.0 v reg?lato? inp?t @ v ldo = 1.5 v ?0 ?5 c ldo exte?nal filte? capacito? val ?e fo? inte?nal co?e powe? s?ppl? the capacito? val?e is dependent on the co?e powe? c???ent con - s?mption 1 ?.? f rev. 1.00 30 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics power consumption table 8. power consumption characteristics t a = ?5 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit i dd s?ppl? c???ent (r?n mode) v dd = 3.3 v ? hsi = ? mhz? pll = 60 mhz ? f hclk = 60 mhz? f pclk = 60 mhz? all pe?iphe?als enabled 14 ma v dd = 3.3 v ? hsi = ? mhz? pll = 60 mhz ? f hclk = 60 mhz? f pclk = 60 mhz? all pe?iphe?als disabled 6.? ma v dd = 3.3 v ? hsi = ? mhz? pll = 40 mhz ? f hclk = 40 mhz? f pclk = 40 mhz? all pe?iphe?als enabled 11. ? ma v dd = 3.3 v ? hsi = ? mhz? pll = 40 mhz ? f hclk = 40 mhz? f pclk = 40 mhz? all pe?iphe?als disabled 6.5 ma v dd = 3.3 v ? hsi = ? mhz? pll = ?0 mhz? f hclk = ?0 mhz? f pclk = ?0 mhz? all pe?iphe?als enabled 5.? ma v dd = 3.3 v ? hsi = ? mhz? pll = ?0 mhz? f hclk = ?0 mhz? f pclk = 60 mhz? all pe?iphe?als disabled 3.? ma v dd = 3.3 v ? hsi = ? mhz? pll off? f hclk = ? mhz? f pclk = ? mhz? all pe?iphe?als enabled 3.? ma v dd = 3.3 v ? hsi = ? mhz? pll off? f hclk = ? mhz? f pclk = ? mhz? all pe?iphe?als disabled 1.4 ma v dd = 3.3 v ? hsi off? pll off? lsi on? f hclk = 3? khz? f pclk = 3? khz? all pe?iphe?als enabled ?3 a v dd = 3.3 v ? hsi off? pll off? lsi on? f hclk = 3? khz? f pclk = 3 ? khz ? all pe? iphe? als disabled 19.5 a rev. 1.00 31 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics electrical characteristics symbol parameter conditions min. typ. max. unit i dd s?ppl? c???ent (sleep mode) v dd = 3.3 v ? hsi = ? mhz? pll = 60 mhz ? f hclk = 0 mhz? f pclk = 60 mhz? all pe?iphe?als enabled 9.0 ma v dd = 3.3 v ? hsi = ? mhz? pll = 60 mhz ? f hclk = 0 mhz? f pclk = 60 mhz? all pe?iphe?als disabled 1.? ma v dd = 3.3 v ? hsi = ? mhz? pll = 40 mhz ? f hclk = 0 mhz? f pclk = 40 mhz? all pe?iphe?als enabled 6.? ma v dd = 3.3 v ? hsi = ? mhz? pll = 40 mhz ? f hclk = 0 mhz? f pclk = 40 mhz? all pe?iphe?als disabled 1.0 ma v dd = 3.3 v ? hsi = ? mhz? pll = ?0 mhz? f hclk = 0 mhz? f pclk = ?0 mhz? all pe?iphe?als enabled 3.7 ma v dd = 3.3 v ? hsi = ? mhz? pll = ?0 mhz? f hclk = 0 mhz? f pclk = ?0 mhz? all pe?iphe?als disabled 0.? ma v dd = 3.3 v ? hsi = ? mhz? pll off? f hclk = 0 mhz? f pclk = ? mhz? all pe?iphe?als enabled ?.9 ma v dd = 3.3 v ? hsi = ? mhz? pll off? f hclk = 0 mhz? f pclk = ? mhz? all pe?iphe?als disabled 0.5 ma s?ppl? c???ent (deep-sleep1 mode) v dd = 3.3 v ? all clock off (hsi/pll/f hclk )? ldo in low powe? mode? lsi on? rtc on 16 a s?ppl? c???ent (deep-sleep? mode) v dd = 3.3 v ? all clock off (hsi/pll/f hclk )? ldo off dmos on? lsi on? rtc on 4.0 a s?ppl? c???ent (powe?-down mode) v dd = 3.3 v ? ldo off? dmos off? lse on? rtc on? lsi on 1.? a v dd = 3.3 v ? ldo off? dmos off? lse off ? rtc off? lsi on 1.1 a note: 1. hse means high speed exte?nal oscillato? . hsi means ? mhz high speed inte?nal oscillato? . ? . lse means 3?.76? khz low speed exte?nal oscillato? . lsi means 3 ? khz low speed inte?nal oscillato? . 3. rtc means ?eal time clock. 4. code = while (1) { ?0? nop } exec?ted in flash. rev. 1.00 3? of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics reset and supply monitor characteristics table 9. v dd power reset characteristics t a = ?5 ?c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dd ope? ation voltage t a = -40 ?c ~ ?5 ?c 0.6 3.6 v v por powe? on reset th?eshold (rising voltage on v dd ) t a = -40 ?c ~ ?5 ?c 1.40 1.55 1.65 v v pdr powe? down reset th?eshold (falling voltage on v dd ) t a = -40 ?c ~ ?5 ?c 1.?7 1.45 1.57 v v porhyst por h?ste?esis 100 mv t por reset dela ? time v dd = 3.3 v 0.1 0.? ms note: 1. data based on cha?acte?ization ?es?lts onl ?? not tested in p?od?ction. ?. g?a?anteed b? design? not tested in p?od?ction. 3. if the ldo is t ?? ned on? the vdd por has to be in the de-asse? tion condition. when the vdd por is in the asse?tion state then the ldo will be t?? ned off. table 10. lvd/bod characteristics t a = ?5 ?c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v bod voltage of b ?own o?t detection afte? facto??-t?immed v dd falling edge 1.6? 1.6? 1.74 v v dd rising edge 1.6? 1.74 1.? v bodhtst bod h?ste?esis v dd = ?.0 v 60 mv v lvd voltage of low voltage detection v dd falling edge lvds = 000 1.67 1.75 1.?3 v lvds = 001 1.?7 1.95 ?.03 v lvds = 010 ?.07 ?.15 ?.?3 v lvds = 011 ?.?7 ?.35 ?.43 v lvds = 100 ?.47 ?.55 ?.63 v lvds = 101 ?.67 ?.75 ?.?3 v lvds = 110 ?.?7 ?.95 3.03 v lvds = 111 3.07 3.15 3.?3 v v lvdhtst lvd h ?ste?esis v dd = 3.3 v 100 mv t s? lvd lvd set ? p time v dd = 3.3 v 5 s t atlvd lvd active dela ? time v dd = 3.3 v s i ddlvd ope ? ation c ??? ent (3) v dd = 3.3 v 5 15 a note: 1. data based on cha?acte?ization ?es?lts onl ?? not tested in p?od?ction. ?. g?a?anteed b? design? not tested in p?od?ction. 3. bandgap c???ent is not incl?ded. 4. lvds feld is in the pwrcu lvdcsr register. rev. 1.00 33 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics electrical characteristics external clock characteristics table 11. high speed external clock (hse) characteristics t a = ?5 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dd ope?ation range 1.65 3.6 v f hse high speed exte?nal oscillato? f?eq?enc? (hse) 4 16 mhz c lhse load capacitance v dd = 3.3 v ? r esr = 100 @ 16 mhz ?? pf r fhse inte?nal feedback resisto? between xtalin and xtalout pins 1 m r esr eq?ivalent se?ies resistance v dd = 3.3 v ? c l = 1? pf @ 16 mhz? hsedr = 0 160 v dd = ?.4 v ? c l = 1? pf @ 16 mhz? hsedr = 1 d hse hse oscillato? d?t? c?cle 40 60 % i ddhse hse oscillato? c???ent cons?mption v dd = 3.3 v @ 16 mhz tbd ma i pwdhse hse oscillato? powe? down c???ent v dd = 3.3 v 0.01 a t suhse hse oscillato? sta?t? p time v dd = 3.3 v 4 ms table 12. low speed external clock (lse) characteristics t a = ?5 ?c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dd ope?ation range 1.65 3.6 v f ck_lse lse f?eq?enc? v bak = 1.65 v ~ 3.6 v 3?.76? khz r f inte?nal feedback resisto? 10 m? r esr eq ? ivalent se? ies resistance v bak = 3.3 v 30 tbd k? c l recommended load capacitances v bak = 3.3 v 6 tbd pf i ddlse oscillato? s?ppl? c???ent (high c???ent mode) f ck_lse = 3?.76? khz? r esr = 50 k?, c l 7 pf v dd = 1.65 v ~ ?.7 v t a = -40 ?c ~ +85 ?c 3.3 6.3 a oscillato? s?ppl? c???ent (low c???ent mode) f ck_lse = 3?.76? khz? r esr = 50 k?, c l < 7 pf v dd = 1.65 v ~ 3.6 v t a = -40 ?c ~ +85 ?c 1.? 3.3 a powe? down c???ent 0.01 a t s?lse sta?t? p time ( low c???ent mode) f ck_lsi = 3?.76? khz? v dd = 1.65 v ~ 3.6 v 500 ms note: the following g ? idelines a?e ? ecommended to inc?ease the stabilit? of the c??stal ci?c?it of the hse / lse clock in the pcb la?o?t: 1. the c ??stal oscillato? sho? ld be located as close as possible to the mcu to keep the t?ace lengths as sho?t as possible to ?ed?ce an? pa?asitic capacitance. rev. 1.00 34 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics ? . shield lines in the vicinit ? of the c?? stal b? ? sing a g?o? nd plane to isolate signals and ?ed?ce noise. 3. keep an ? high f?eq?enc? signal lines awa? f? om the c?? stal a? ea to p? event an? c? osstalk adve? se effects. internal clock characteristics table 13. high speed internal clock (hsi) characteristics t a = ?5 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dd ope?ation range 1.65 3.6 v f hsi hsi f?eq?enc? v dd = 3.3 v ? t a = ?5 ?c ? mhz acc hsi facto?? calib?ated hsi oscillato? f?eq?enc? acc??ac? v dd = 3.3 v ? t a = ?5 ?c -? ? % v dd = ?.5 v ~ 3.6 v ? t a = -40 ?c ~ +?5 ?c -3 3 % v dd = 1.65 v ~ 3.6 v t a = -40 ?c ~ +?5 ?c -6 6 % d?t? d?t? c?cle f hsi = ? mhz 35 65 % i ddhsi oscillato? s?ppl? c???ent f hsi = ? mhz 300 500 a powe? down c???ent 0.05 a t s?hsi sta?t? p time f hsi = ? mhz 10 s table 14. low speed internal clock (lsi) characteristics t a = ?5 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dd ope?ation range 1.65 3.6 v f lsi low speed inte?nal oscillato? f?eq?enc? (lsi) v dd = 3.3 v ? t a = -40 ?c ~ +85 ?c ?1 3? 43 khz acc lsi lsi f ?eq?enc? acc??ac? afte? facto??-t?immed? v dd = 3.3 v ? t a = ?5 ?c -10 +10 % i ddlsi lsi oscillato? ope?ating c???ent v dd = 3.3 v ? t a = ?5 ?c 0.4 0.? a t sulsi lsi oscillato? sta?t? p time v dd = 3.3 v ? t a = ?5 ?c 100 s pll characteristics table 15. pll characteristics t a = ?5 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit f pllin pll inp ?t clock 4 16 mhz f ck_pll pll o ?tp?t clock 16 60 mhz t lock pll lock time ?00 s rev. 1.00 35 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics electrical characteristics usb pll characteristics table 16. usb pll characteristics t a = ?5 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit f pllin pll inp ?t clock 4 16 mhz f ck_pll pll o ?tp?t clock 16 4? mhz t lock pll lock time ?00 s memory characteristics table 17. flash memory characteristics t a = ?5 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit n endu n?mbe? of g?a?anteed p?og?am/e?ase c?cles befo?e fail??e (end??ance) t a = -40 ?c ~ +?5 ?c 10 k c?cles t ret data retention time t a = -40 ?c ~ +?5 ?c 10 yea ?s t prog wo ? d p?og? amming time t a = -40 ?c ~ +?5 ?c ?0 s t erase page e ? ase time t a = -40 ?c ~ +?5 ?c ? ms t merase mass e ? ase time t a = -40 ?c ~ +?5 ?c 10 ms i/o port characteristics table 18. i/o port characteristics v dd = 3.3 v ? t a = ?5 ?c, unless otherwise specifed. symbol parameter conditions min. typ. max. unit i il low level inp?t c???ent 3.3 v io v i = v ss ? on-chip p?ll-?p ?esiste? disabled. 3 a reset pin 3 a i ih high level inp?t c???ent 3.3 v io v i = v dd? on-chip p?ll-down ?esiste? disabled. 3 a reset pin 3 a v il low level inp?t voltage 3.3 v io -0.5 v dd 0.35 v reset pin -0.5 v dd 0.35 v v ih high level inp?t voltage 3.3 v io v dd 0.65 v dd + 0.5 v reset pin v dd 0.65 v dd + 0.5 v v hys schmitt t ?igge? inp?t voltage h ?ste?esis 3.3 v io 0.1? v dd mv reset pin 0.1? v dd mv rev. 1.00 36 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics symbol parameter conditions min. typ. max. unit i ol low level o?tp?t c???ent (gpio sink c???ent) 3.3 v io 4 ma d ?ive? v ol = 0.4 v 4 ma 3.3 v io ? ma d?ive? v ol = 0.4 v ? ma 3.3 v io 1? ma d?ive? v ol = 0.4 v 1? ma 3.3 v io 16 ma d ?ive? v ol = 0.4 v 16 ma i oh high level o?tp?t c??? ent (gpio so?? ce c???ent) 3.3 v i/o 4 ma d ?ive? v oh = v dd - 0.4 v 4 ma 3.3 v i/o ? ma d?ive? v oh = v dd - 0.4 v ? ma 3.3 v i/o 1? ma d?ive? v oh = v dd - 0.4 v 1? ma 3.3 v i/o 16 ma d ?ive? v oh = v dd - 0.4 v 16 ma v ol low level o?tp?t voltage 3.3 v 4 ma d ?ive io? i ol = 4 ma 0.4 v 3.3 v ? ma d?ive io? i ol = ? ma 0.4 v 3.3 v 1? ma d?ive io? i ol = 1? ma 0.4 v 3.3 v 16 ma d ?ive io? i ol = 16 ma 0.4 v v oh high level o?tp?t voltage 3.3 v 4 ma d ?ive io? i oh = 4 ma v dd - 0.4 v 3.3 v ? ma d?ive io? i oh = ? ma v dd - 0.4 v 3.3 v 1? ma d?ive io? i oh = 1? ma v dd - 0.4 v 3.3 v 16 ma d ?ive io? i oh = 16 ma v dd - 0.4 v r pu inte?nal p?ll-up resisto? 3.3 v i/o? v dd = 3.3 v 60 k r pd inte?nal p?ll-down resisto? 3.3 v i/o? v dd = 3.3 v 60 k pwm/gptm characteristics table 19. gptm characteristics symbol parameter conditions min. typ. max. unit f tm time ? clock f?eq?enc? f pclk mhz t res time ? resol? tion time 1 f tm f ext exte?nal single f?eq?enc? on channel 1 ~ 4 1/? f tm res time ? resol?tion 16 bits rev. 1.00 37 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics electrical characteristics i 2 c characteristics table 20. i 2 c characteristics symbol parameter standard mode fast mode fast mode plus unit min. max. min. max. min. max. f scl scl clock f ?eq?enc? 100 400 1000 khz t scl(h) scl clock high time 4.5 1.1?5 0.45 s t scl(l) scl clock low time 4.5 1.1?5 0.45 s t fall scl and sda fall time 1.3 0.34 0.135 s t rise scl and sda rise time 1.3 0.34 0.135 s t su(sda) sda data set ? p time 500 1?5 50 ns t h(sda) sda data hold time 0 0 0 ns t su(sta) start condition set ?p time 500 1?5 50 ns t h(sta) start condition hold time 0 0 0 ns t su(sto) stop condition set ?p time 500 1?5 50 ns note: 1. g?a?anteed b? design? not tested in p?od?ction. ? . to achieve 100 khz standa?d mode? the pe?iphe?al clock f?eq?enc? m?st be highe? than ? mhz. 3. to achieve 400 khz fast mode ? the pe?iphe?al clock f?eq?enc? m?st be highe? than ? mhz. 4. to achieve 1 mhz fast mode pl ?s? the pe?iphe?al clock f?eq?enc? m?st be highe? than ?0 mhz. 5. the above cha ?acte?istic pa?amete?s of the i ? c b?s timing a?e based on : seq_filter = 01 and comb_filter_en is disabled. t su(sta) t h(sta) t fall t scl(l) t rise t scl(h) t h(sda) t su(sda) t su(sto) scl sda figure 8. i 2 c timing diagrams rev. 1.00 3? of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics spi characteristics table 21. spi characteristics symbol parameter conditions min. typ. max. unit spi master mode f sck (1/t sck ) spi maste? o?tp?t sck clock f?eq?enc? maste? mode spi pe?iphe?al clock f?eq?enc? f pclk f pclk /? mhz t sck(h) t sck(l) sck clock high and low time t sck /? - ? t sck /? + 1 ns t v(mo) data o?tp? t valid time 5 ns t h(mo) data o?tp? t hold time ? ns t su(mi) data inp?t set? p time 5 ns t h(mi) data inp? t hold time 5 ns spi slave mode f sck (1/t sck ) spi slave inp?t sck clock f?eq?enc? slave mode spi pe?iphe?al clock f?eq?enc? f pclk f pclk /3 mhz d?t? sck spi slave inp?t sck clock d?t? c?cle 30 70 % t su(sel) sel enable set ? p time 3 t pclk ns t h(sel) sel enable hold time ? t pclk ns t a(so) data o ?tp? t access time 3 t pclk ns t dis(so) data o?tp? t disable time 10 ns t v(so) data o?tp? t valid time ?5 ns t h(so) data o?tp? t hold time 15 ns t su(si) data inp?t set? p time 5 ns t h(si) data inp? t hold time 4 ns note: t sck = 1/f sck ; t pclk = 1/f pclk . spi o?tp?t (inp?t) clock f?eq?enc? : f sck ; spi pe?iphe?al clock f?eq?enc? : f pclk . rev. 1.00 39 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics electrical characteristics sck (cpol=0) sck (cpol=1) mosi miso mosi miso t sck t sck(h) t sck(l) data valid data valid data valid t su(mi) t v(mo) t h(mo) t h(mi) data valid data valid data valid t v(mo) t h(mo) data valid data valid data valid data valid data valid data valid t su(mi) t h(mi) cpha=1 cpha=0 figure 9. spi timing diagrams C spi master mode sck (cpol=0) sck (cpol=1) mosi miso t sck t sck(h) t sck(l) msb/lsb in t h(si) t su(sel) t h(sel) t su(si) lsb/msb in msb/lsb out lsb/msb out t a(so) t v(so) t h(so) t dis(so) sel figure 10. spi timing diagrams C spi slave mode with cpha=1 rev. 1.00 40 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics usb characteristics the usb interface is usb-if certifed - full speed. table 22. usb dc electrical characteristics symbol parameter conditions min. typ. max. unit v dd usb ope? ating voltage 3.0 3.6 v v di diffe ?ential inp?t sensitivit? |usbdp C usbdm| 0.? v v cm common mode voltage range 0.? ?.5 v v se single-ended receive ? th?eshold 0.? ?.0 v v ol pad o?tp? t low voltage r l rinwr9 dd33 0 0.3 v v oh pad o?tp? t high voltage ?.? 3.6 v v crs diffe ?ential o?tp?t signal c?oss- point voltage 1.3 ?.0 v z drv d?ive? o?tp?t resistance 10 c in t ?ansceive? pad capacitance ?0 pf note: 1. g?a?anteed b? design? not tested in p?od?ction. ? . the usb f?nctionalit? is ens??ed down to ?.7 v b?t not the f?ll usb elect?ical cha?acte?istics which will expe?ience deg?adation in the ?.7 v to 3.0 v v dd voltage ?ange. 3. rl is the load connected to the usb d?ive? usbdp. t ? t f 90% 90% 10% 10% fall time rise time v crs figure 11. usb signal rise time and fall time and cross-point voltage (v crs ) defnition table 23. usb ac electrical characteristics symbol parameter conditions min. typ. max. unit t ? rise time c l = 50 pf 4 ?0 ns t f fall time c l = 50 pf 4 ?0 ns t ?/f rise time / fall time matching t ?/f = t ? / t f 90 110 % rev. 1.00 41 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? electrical characteristics package information 6 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. package information (include outline dimensions, product tape and reel specifcations) the operation instruction of packing materials carton information rev. 1.00 4? of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? package information saw type 24-pin qfn (3mm3mm0.55mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.0?0 0.0?? 0.0?4 a1 0.000 0.001 0.00? a3 0.006 bsc b 0.006 0.00? 0.010 b1 0.014 0.016 0.01? d 0.11 ? bsc e 0.11 ? bsc e 0.016 bsc e1 0.0?0 bsc d? 0.073 0.075 0.077 e? 0.073 0.075 0.077 l 0.006 0.010 0.014 l1 0.00? 0.010 0.01? k 0.00? symbol dimensions in mm min. nom. max. a 0.50 0.55 0.60 a1 0.00 0.0? 0.05 a3 0.150 bsc b 0.15 0.?0 0.?5 b1 0.35 0.40 0.45 d 3.00 bsc e 3.00 bsc e 0.40 bsc e1 0.50 bsc d? 1.?5 1.90 1.95 e? 1.?5 1.90 1.95 l 0.15 0.?5 0.35 l1 0.?0 0.?5 0.30 k 0.?0 rev. 1.00 43 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? package information package information saw type 33-pin qfn (4mm4mm) outline dimensions 33 symbol dimensions in inch min. nom. max. a 0.0?? 0.030 0.031 a1 0.000 0.001 0.00? a3 0.00? bsc b 0.006 0.00? 0.010 d 0.157 bsc e 0.157 bsc e 0.016 bsc d? 0.104 0.106 0.10? e? 0.104 0.106 0.10? l 0.014 0.016 0.01? k 0.00? symbol dimensions in mm min. nom. max. a 0.70 0.75 0.?0 a1 0.00 0.0? 0.05 a3 0.?03 bsc b 0.15 0.?0 0.?5 d 4.00 bsc e 4.00 bsc e 0.40 bsc d? ?.65 ?.70 ?.75 e? ?.65 ?.70 ?.75 l 0.35 0.40 0.45 k 0.?0 rev. 1.00 44 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? package information saw type 46-pin qfn (6.5mm4.5mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.031 0.033 0.035 a1 0.000 0.001 0.00? a3 0.00? bsc b 0.006 0.00? 0.010 d 0.?54 0.?56 0.?5? e 0.175 0.177 0.179 e 0.016 bsc d? 0.197 0.?01 0.?05 e? 0.11 ? 0.1?? 0.1?6 l 0.01? 0.016 0.0?0 symbol dimensions in mm min. nom. max. a 0.?0 0.?5 0.90 a1 0.00 0.0? 0.04 a3 0.?0 bsc b 0.15 0.?0 0.?5 d 6.45 6.50 6.55 e 4.45 4.50 4.55 e 0.40 bsc d? 5.00 5.10 5.?0 e? 3.00 3.10 3.?0 l 0.30 0.40 0.50 rev. 1.00 45 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? package information package information 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.354 bsc b 0.?76 bsc c 0.354 bsc d 0.?76 bsc e 0.0?0 bsc f 0.007 0.009 0.011 g 0.053 0.055 0.057 h 0.063 i 0.00? 0.006 ? 0.01? 0.0?4 0.030 k 0.004 0.00? 0 D 7 symbol dimensions in mm min. nom. max. a 9.0 bsc b 7.0 bsc c 9.0 bsc d 7.0 bsc e 0.5 bsc f 0.17 0.?? 0.?7 g 1.35 1.4 1.45 h 1.60 i 0.05 0.15 ? 0.45 0.60 0.75 k 0.09 0.?0 0 D 7 rev. 1.00 46 of 46 ?an?a?? 11? ?01? 3?-bit a?m ? co?tex ? -m0+ mcu ht3?f000? package information cop??ight ? ?01? b? holtek semiconductor inc. the info ? mation appea? ing in this data sheet is believed to be acc?? ate at the time of p?blication. howeve ?? holtek ass?mes no ?esponsibilit? a?ising f?om the ? se of the specifications desc? ibed. the applications mentioned he?ein a?e ?sed solel? fo? the p ?? pose of ill?st? ation and holtek makes no wa??ant? o? ?ep? esentation that s? ch applications will be s?itable witho?t f??the? modification? no? ?ecommends the ? se of its p ?od? cts fo? application that ma? p? esent a ? isk to h? man life d? e to malf ? nction o? othe?wise. holtek's p?od?cts a?e not a?tho?ized fo? ?se as c? itical components in life s?ppo? t devices o? s? stems. holtek ?ese? ves the ? ight to alte? its p?od? cts witho? t p?io? notifcation. for the most up-to-date information, please visit our web site at http://www. holtek.com/en/. |
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